1. Field of the Invention
The present invention relates to a lead frame and a package, and more particularly a bottom lead frame and a bottom lead semiconductor package using the same.
2. Description of the Related Art
Semiconductor packages are typically classified into a small outline package (SOP), a small outline J-leaded package (SOJ), a quad flat package (QFP), etc. The common characteristic of the above-described semiconductor packages are that inner leads, through which external connections are made to a chip, project from the package body.
In the conventional semiconductor packages, there are problems in that an area occupied by the packages is relatively large compared to the size of the substrate because the inner leads extend laterally from the sides of the package body. Also, the semiconductor packages are often harmed when mounting the chip on the substrate, thus increasing a defective package ratio, since the inner leads are easily bent.
U.S. Pat. No. 5,428,248 of the same assignee as this application is directed to overcoming the above-described problems. The semiconductor package disclosed in U.S. Pat. No. 5,428,248 is known in the industry as a Bottom Lead Semiconductor Package (BLP). The disclosure of U.S. Pat. No. 5,428,248 is incorporated by reference herein. FIG. 1 illustrates a typical bottom lead semiconductor package. As shown therein, the bottom lead semiconductor package includes a lead frame 13 having a plurality of bottom leads 11, the lower surfaces of which are capable of being connected with a substrate or circuit board (not shown). The bottom leads 11 extend to form inner leads 12, which are upwardly bent from the bottom leads 11. A semiconductor chip 15 is fixed to the upper surfaces of the bottom leads 11 by an adhesive material 14. A plurality of conductive wires 16 electrically connect to a plurality of chip pads 10 of the semiconductor chip 15 and the inner leads 12 of the lead frame 13. The conductive wires 16, the semiconductor chip 15, the bottom leads 11 and the inner leads 12 of the lead frame 13 are packaged in a molding resin 17, except for the lower surfaces of the bottom leads 11, which are exposed to the outside of the package body. The exposed bottom leads 11 may be covered by a lead coating 18.
In the bottom lead semiconductor package described above, the size of the chip package increases as the number of leads increases, resulting in an increase in the substrate occupying area. Such increase is disadvantageous.